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document number: mc33932 rev. 3.0, 1/2009 freescale semiconductor advance information * this document contains certain information on a new product. specifications and information herein are subject to change without notice. ? freescale semiconductor, in c., 2009. all rights reserved. 5.0 a throttle control h-bridge the 33932 is a monolithic h-bridge power ic in a robust thermally enhanced package. the 33932 has two independent monolithic h- bridge power ics in the same package. they are designed primarily for automotive electronic throttle contro l, but are applicable to any low- voltage dc servo motor control application within the current and voltage limits stated in this specification. each h-bridge in the 33932 is able to control inductive loads with currents up to 5.0 a peak. rms current capability is subject to the degree of heatsinking provided to the device package. internal peak- current limiting (regulation) is activated at load currents above 6.5 a 1.5 a. output loads can be pulse width modulated (pwm-ed) at frequencies up to 11 khz. a load current feedback feature provides a proportional (0.24% of the load current) current output suitable for monitoring by a microcontroller?s a/d input. a status flag output reports under-voltage, over-curr ent, and over-temperature fault conditions. two independent inputs provide polarity control of two half-bridge totem-pole outputs. two independent disable inputs are provided to force the h-bridge outputs to tr i-state (high-imped ance off-state). features ? 8.0 to 28 v continuous operation (trans ient operation from 5.0 to 40 v) ? 235 m maximum r ds(on) @ 150c (each h-bridge mosfet) ?3.0 v and 5.0 v ttl / cmos logic compatible inputs ? over-current limiting (regulation) via internal constant-off-time pwm ? output short-circuit protection (short to vpwr or gnd) ? temperature-dependant current-limit threshold reduction ? all inputs have an internal source/sink to define the default (f loating input) states ? sleep mode with current draw < 50 a (each half with inputs floating or set to match default logic states) figure 1. mc33932 simplified application diagram throttle cont rol h-bridge 33932 ordering information device temperature range (t a ) package mc33932vw/r2 -40c to 125c 44 hsop vw suffix (pb-free) 98arh98330a 44-pin hsop with protruding heat sink sfa fba in1 in2 d1 en/d2 vpwra ccpa out1 out2 pgnda agnda mcu 33932 v pwr v dd motor out3 out4 motor sfb in4 in3 fbb d3 en/d4 pgndb agndb vpwrb ccpb v pwr v dd
analog integrated circuit device data 2 freescale semiconductor 33932 internal block diagram internal block diagram figure 2. 33932 simplifi ed internal block diagram vdd logic supply charge pump gate drive and protection logic current mirror and constant off-time pwm current regulator vcp ccpa out1 out2 pgnda to gates hs1 ls1 hs2 ls2 vpwra vsense ilim pwm hs1 hs2 ls1 ls2 ls2 in1 in2 en/d2 d1 sfa fba agnda pgnd vdd logic supply charge pump gate drive and protection logic current mirror and constant off-time pwm current regulator vcp ccpb pgndb to gates hs1 ls1 hs2 ls2 vpwrb vsense ilim pwm hs1 hs2 ls1 ls2 ls2 in3 in4 en/d4 d3 sfb fbb agndb pgnd out3 out4 h-bridge a h-bridge b
analog integrated circuit device data freescale semiconductor 3 33932 pin connections pin connections figure 3. 33932 pin connections table 1. 33932 pin definitions a functional description of each pin can be found in the functional description section beginning on page 11 . pin pin name pin function formal name definition 1 d1 logic input disable input 1 (active high) when d1 is logic high, both out1 and out2 are tri-stated. schmitt trigger input with ~80 a source so default condition = disabled. 2 fba analog output feedback h-bridge a load current feedback output provides ground referenced 0.24% of the high side output current. (tie to gnd through a resistor if not used.) 3 en/ d2 logic input enable input when en/ d2 is logic high, h-bridge a is operational. when en/ d2 is logic low, the h-bridge a outputs are tri-stated and h-bridge a is placed in sleep mode. (logic input with ~ 80 a sink so default condition = sleep mode.) 4-6,39,40 v pwra vpwrb power input positive power supply these pins must be connected together physically as cl ose as possible and directly soldered down to a wide, th ick, low resistance supply plane on the pcb. 7-9 out1 power output h-bridge output 1 h-bridge a source of high side mosfet1 and drain of low side mosfet1. 10,11,34,35 pgnda power ground power ground high-current power ground pins must be connected together physically as close as possible and directly soldered down to a wide, thick, low resistance ground plane on the pcb. 12,13,32,33 pgndb power ground power ground high-current power ground pins must be connected together physically as close as possible and directly soldered down to a wide, thick, low resistance ground plane on the pcb. tab tab h-bridge a h-bridge b 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 d1 fba en/d2 vpwra vpwra vpwra out1 out1 out1 pgnda pgnda sfa in1 in2 ccpa vpwra vpwra out2 out2 out2 pgnda pgnda 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 d3 fbb en/d4 vpwrb vpwrb vpwrb out3 out3 out3 pgndb pgndb sfb in3 in4 ccpb vpwrb vpwrb out4 out4 out4 pgndb pgndb agnda agndb
analog integrated circuit device data 4 freescale semiconductor 33932 pin connections 14-16 out4 power output h-bridge output 4 h-bridge b source of high side mo sfet2 and drain of low side mosfet2. 17,18,26-28 vpwrb power input positive power supply these pins must be connected together physically as cl ose as possible and directly soldered down to a wide, th ick, low resistance supply plane on the pcb. 19 ccpb analog output charge pump capacitor external reservoir capacit or connection for h-bridge b internal charge pump; connected to vpwrb. allowable values are 30 to 100 nf. note: this capacitor is required for the proper performance of the device. 20 in4 logic input input 4 logic input control of out4. 21 in3 logic input input 3 logic input control of out3. 22 sfb logic output - open drain status flag b (active low) h-bridge b open drain active low status flag output (requires an external pull- up resistor to v dd . maximum permissible load current < 0.5 ma. maximum v cesat < 0.4 v @ 0.3 ma. maximum permissible pull-up voltage < 7.0 v.) 23 d3 logic input disable input 3 (active high) when d3 is logic high, both out3 and out4 are tri-stated. schmitt trigger input with ~80 a source so default condition = disabled. 24 fbb analog output feedback b h-bridge b load current feedback output provides ground referenced 0.24% of the high side output current. (tie to gnd through a resistor if not used.) 25 en/ d4 logic input enable input when en/ d4 is logic high, h-bridge b is operational. when en/ d4 is logic low, the h-bridge b outputs are tri-stated and h-bridge b is placed in sleep mode. (logic input with ~ 80 a sink so default condition = sleep mode.) 29-31 out3 power output h-bridge output 3 h-bridge b source of high side mo sfet1 and drain of low side mosfet1. 36-38 out2 power output h-bridge output 2 h-bridge a source of high side mosfet 2 and drain of low side mosfet2. 41 ccpa analog output charge pump capacitor external reservoir capacit or connection for h-bridge a internal charge pump; connected to vpwra. allowable values are 30 to 100 nf. note: this capacitor is required for the proper performance of the device. 42 in2 logic input input 2 logic input control of out2. 43 in1 logic input input 1 logic input control of out1; e.g., when in1 is logic high, out1 is set to vpwra, and when in1 is logic low, out1 is set to pgnda. (schmitt trigger input with ~ 80 a source so default condition = out1 high.) 44 sfa logic output - open drain status flag (active low) h-bridge a open drain active low status flag output (requires an external pull-up resistor to v dd . maximum permissible load current < 0.5 ma. maximum v cesat < 0.4 v @ 0.3 ma. maximum permissible pull-up voltage < 7.0 v.) tab agnda agndb analog ground analog signal ground the low-current analog signal ground must be connected to pgnd via low- impedance path (<<10 m , 0 hz to 20 khz). exposed tab is also the main heatsinking path for the device. table 1. 33932 pin de finitions (continued) a functional description of each pin can be found in the functional description section beginning on page 11 . pin pin name pin function formal name definition
analog integrated circuit device data freescale semiconductor 5 33932 electrical characteristics maximum ratings electrical characteristics maximum ratings table 2. maximum ratings all voltages are with respect to ground unless otherwise no ted. exceeding these ratings may cause a malfunction or permanent damage to the device. thes e parameters are not production tested. ratings symbol value unit electrical ratings power supply voltage normal operation (steady-state) transient overvoltage (1) v pwr(ss) v pwr(t) - 0.3 to 28 - 0.3 to 40 v logic input voltage (2) v in - 0.3 to 7.0 v sfa , sfb output (3) v sf - 0.3 to 7.0 v continuous output current (4) i out(cont) 5.0 a esd voltage (5) human body model machine model charge device model corner pins (1,9,17,25) all other pins v esd1 v esd2 2000 200 750 500 v thermal ratings storage temperature t stg - 65 to 150 c operating temperature (6) ambient junction t a t j - 40 to 125 - 40 to 150 c peak package reflow temperature during reflow (7) , (8) t pprt note 8 c approximate junction-to case thermal resistance (9) r thjc <1.0 c/w notes 1. device will survive repetitive transient over-v oltage conditions for durations not to exceed 500ms @ duty cycle not to exceed 10%. external protection is required to prevent devic e damage in case of a reverse battery condition. 2. exceeding the maximum input voltage on in1, in2, in3, in4, en/ d2 , en/ d4 , d1, or d3 may cause a malfunction or permanent damage to the device. 3. exceeding the pull-up resistor voltage on the open drain sfa or sfb pin may cause permanent damage to the device. 4. continuous output current capability is dependent on suffi cient package heatsinking to keep junction temperature 150 c. 5. esd testing is performed in accordance with the human body model (c zap = 100 pf, r zap = 1500 ), machine model (c zap = 200 pf, r zap = 0 ), and the charge device model (cdm), robotic (c zap = 4.0 pf). 6. the limiting factor is junction temperatur e, taking into account the power dissipat ion, thermal resistance, and heat sinking provided. brief non-repetitive excursions of junction temperature above 150 c can be tolerated, provided the duration does not exceed 30 seconds maximum. (non-repetitive events are defined as not occurring more than once in 24 hours.) 7. pin soldering temperature limit is for 10 seconds maximum dura tion. not designed for immersion so ldering. exceeding these lim its may cause malfunction or permanent damage to the device. 8. freescale?s package reflow capability m eets pb-free requirements for jedec standard j-std-020c. for peak package reflow temperature and moisture sensitivity levels (msl), go to www.free scale.com, search by part number [e.g. remove prefixes/suffixe s and enter the core id to view all orderable parts. (i.e. mc33xxxd enter 33xxx), and review parametrics. 9. exposed heatsink pad plus the power and ground pins comprise the main heat conduction paths. the actual r jb (junction-to-pc board) values will vary depending on solder thickness and composition and copper trace thickness and area. maximum current at maximum die temperature represents ~16 w of conduction loss heating in the diagonal pair of output mosfets. therefore, the r ja must be < 5.0 c/w for maximum current at 70 c ambient. module thermal desi gn must be planned accordingly.
analog integrated circuit device data 6 freescale semiconductor 33932 electrical characteristics static electrical characteristics static electrical characteristics table 3. static electric al characteristics characteristics noted under conditions 8.0 v v pwr 28 v, - 40 c t a 125 c, gnd = 0 v, unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25c under nominal conditi ons, unless otherwise noted. specifications given for h-bridge a apply symmetrically to h-bridge b. characteristic symbol min typ max unit power inputs (vpwr) operating voltage range (10) steady-state transient (t < 500 ms) (11) quasi-functional (r ds(on) may increase by 50%) v pwr(ss) v pwr(t) v pwr(qf) 8.0 ? 5.0 ? ? ? 28 40 8.0 v sleep state supply current (12) en/ d2 = logic [0], in1, in2, d1 = logic [1], and i out = 0 a i pwr(sleep) ? ? 50 a standby supply current (part enabled) i out = 0 a, v en = 5.0 v i pwr(standby) ? ? 20 ma under-voltage lockout thresholds v pwr(falling) v pwr(rising) hysteresis v uvlo(active) v uvlo(inactive) v uvlo(hys) 4.15 ? 150 ? ? 200 ? 5.0 350 v v mv charge pump charge pump voltage (cp capacitor = 33 nf), no pwm v pwr = 5.0 v v pwr = 28 v v cp - v pwr 3.5 ? ? ? ? 12 v charge pump voltage (cp capacitor = 33 nf), pwm = 11 khz v pwr = 5.0 v v pwr = 28 v v cp - v pwr 3.5 ? ? ? ? 12 v control inputs operating input voltage (in1, in2, d1, en/ d2 , in3, in4, d3, en/ d4 ) v i ? ? 5.5 v input voltage (in1, in2, d1, en/ d2 , in3, in4, d3, en/ d4 ) logic threshold high logic threshold low hysteresis v ih v il v hys 2.0 ? 250 ? ? 400 ? 1.0 ? v v mv logic input currents, vpwr = 8.0 v input en/ d2 , en/ d4 (internal pull-downs), v ih = 5.0 v inputs in1, in2, d1, in3, in4, d3 (internal pull-ups), vil = 0 v i in 20 -200 80 -80 200 -20 a notes 10. device specifications are char acterized over the range of 8.0 v v pwr 28 v. continuous operation above 28 v may degrade device reliability. device is operational down to 5.0v, but below 8.0 v the output resistance may increase by 50 percent. 11. device will survive the tr ansient over-voltage indicated for a maximum duration of 500 ms. transient not to be repeated more than once every 10 seconds. 12. i pwr(sleep) is with sleep mode activated and en/ d2 , = logic [0], and in1, in2, d1 = logi c [1] or with these inputs left floating.
analog integrated circuit device data freescale semiconductor 7 33932 electrical characteristics static electrical characteristics power outputs out1, out2 output-on resistance (14) , i load = 3.0 a v pwr = 8.0 v, t j = 25 c v pwr = 8.0 v, t j = 150 c v pwr = 5.0 v, t j = 150 c r ds(on) ? ? ? 120 ? ? ? 235 325 m output current regulation threshold t j < t fb t j t fb (fold back region - see figure 9 and figure 11 ) (13) i lim 5.2 ? 6.5 4.2 8.0 ? a high side short circuit detection threshold (short circuit to ground) (13) i sch 11 13 16 a low side short circuit detection threshold (short circuit to v pwr ) (13) i scl 9.0 11 14 a output leakage current (15) , outputs off, v pwr = 28 v v out = v pwr v out = ground i outleak ? ?60 ? ? 100 ? a output mosfet body diode forward voltage drop, i out = 3.0 a v f ? ? 2.0 v over-temperature shutdown (13) thermal limit @ t j hysteresis @ t j t lim t hys 175 ? ? 12 200 ? c current foldback at t j (13) t fb 165 ? 185 c current foldback to thermal shutdown separation (13) t sep 10 ? 15 c high side current sense feedback feedback current (pin fb sourcing current) (16) i out = 0 ma i out = 300 ma i out = 500 ma i out = 1.5 a i out = 3.0 a i out = 6.0 a i fb 0.0 0.0 0.35 2.86 5.71 11.43 ? 270 0.775 3.57 7.14 14.29 50 750 1.56 4.28 8.57 17.15 a a ma ma ma ma status flag (17) status flag leakage current (18) v sf = 5.0 v i sfleak ? ? 5.0 a status flag set voltage (19) i sf = 300 a v sflow ? ? 0.4 v notes 13. this parameter is guaranteed by design. 14. output-on resistance as measured from output to v pwr and from output to gnd. 15. outputs switched off via d1 or en/ d2 . 16. accuracy is better than 20% from 0.5 a to 6.0 a. recommended terminating resistor value: r fb = 270 . 17. status flag output is an open drain output requiring a pull-up resistor to logic v dd . 18. status flag leakage current is measured with status flag high and not set. 19. status flag set voltage measured with status flag low and set with i sf = 300 a . maximum allowable sink current from this pin is < 500 a . maximum allowable pull-up voltage < 7.0 v. table 3. static electrical characteristics (continued) characteristics noted under conditions 8.0 v v pwr 28 v, - 40 c t a 125 c, gnd = 0 v, unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25c under nominal conditi ons, unless otherwise noted. specifications given for h-bridge a apply symmetrically to h-bridge b. characteristic symbol min typ max unit
analog integrated circuit device data 8 freescale semiconductor 33932 electrical characteristics dynamic electrical characteristics dynamic electrical characteristics table 4. dynamic electri cal characteristics characteristics noted under conditions 8.0 v v pwr 28 v, - 40 c t a 125 c, gnd = 0 v, unless otherwise noted. typical values noted reflect the approximate parameter means at t a = 25c under nominal conditions, unless otherwise noted. characteristic symbol min typ max unit timing characteristics pwm frequency (20) f pwm ? ? 11 khz maximum switching frequency during current limit regulation (21) f max ? ? 20 khz output on delay (22) v pwr = 14 v t d on ? ? 18 s output off delay (22) v pwr = 14 v t d off ? ? 12 s i lim output constant-off time (23) t a 15 20.5 32 s i lim blanking time (24) t b 12 16.5 27 s disable delay time (25) t d disable ? ? 8.0 s output rise and fall time (26) t f , t r 1.5 3.0 8.0 s short-circuit / over-temperature turn-off (latch-off) time (27) , (28) t fault ? ? 8.0 s power-on delay time (28) t pod ? 1.0 5.0 ms output mosfet body diode reverse recovery time (28) t r r 75 100 150 ns charge pump operating frequency (28) f cp ? 7.0 ? mhz notes 20. the maximum pwm frequency should be limited to frequencies < 11 khz in order to allow the internal high side driver circuitry time to fully enhance the high side mosfets. 21. the internal current limit circuitry produces a constant-off -time pulse width modulation of the output current. the output l oad?s inductance, capacitance, and resistance char acteristics affect the total switching period (off-time + on-time), and thus the pw m frequency during current limit. 22. * output delay is the time duration from 1.5v on the in1 or in2 input signal to the 20% or 80% point (dependent on the transition direction) of the out1 or out2 signal. if the output is tr ansitioning high-to-low, the delay is from 1.5 v on the input signal to the 80% point of the output response signal. if the output is trans itioning low-to-high, the delay is from 1.5 v on the input signal to the 20% point of the output response signal. see figure 4 , page 9 . 23. the time during which the internal constant-off time pwm current regulation circuit has tri-stated the output bridge. 24. the time during which the current regulation threshold is i gnored so that the short-circuit detection threshold comparators may have time to act. 25. * disable delay time measurement is defined in figure 5 , page 9 . 26. rise time is from the 10% to the 90% level and fall time is from the 90% to the 10% level of the output signal with v pwr = 14 v, r load = 3.0 ohm. see figure 6 , page 9 . 27. load currents ramping up to the current r egulation threshold become limited at the i lim value (see figure 7 ). the short-circuit currents possess a di/dt that ramps up to the i sch or i scl threshold during the i lim blanking time, registering as a short-circuit event detection and causing the shutdown circuitry to force the out put into an immediate tri-state latch-off (see figure 8 ). operation in current limit mode may cause junction temperatures to rise. junction temperatures above ~160 c will cause the output current limit threshold to ?fold back?, or decrease, until ~175 c is reached, after which the t lim thermal latch-off will occur. permissibl e operation within this fold back region is limited to non-repetitive transient event s of duration not to exceed 30 seconds (see figure 9 ). 28. parameter is guaranteed by design.
analog integrated circuit device data freescale semiconductor 9 33932 electrical characteristics timing diagrams timing diagrams figure 4. output delay time figure 5. disable delay time . figure 6. output switching time figure 7. current limit blanking time and constant-off time 5.0 v pwr 0 0 time 1.5 v 1.5 v 20% 80% t don v out1, 2 (v) v in1, in2 (v) t doff 0v 5.0 v 0 v v out1, 2 v d1, en/d2 (v) time 1.5 v tddisable 90% i o = 100ma 90% 90% 10% 10% v out1, 2 (v) t f t r v pwr 0 time i sc short circuit detection threshold i out , current (a) t b 5.0 t a 9.0 0.0 i lim 6.5 t b = i lim blanking time t a = constant-off time (out1 and out2 tri-stated) overload condition t on time
analog integrated circuit device data 10 freescale semiconductor 33932 electrical characteristics timing diagrams figure 8. short-circuit detection turn-off time t fault . figure 9. output current limiting foldback region i sc short-circuit detection threshold i out , current (a) 5.0 9.0 0.0 i lim 6.5 hard short occurs t fault short circuit condition t b (~16 s) t b time sf set low out1, out2 tri-stated, current limit threshold foldback. i lim , current (a) 6.5 4.2 t lim t fb t hys t sep t lim thermal shutdown operation within this region must be limited to non-repetitive events not to exceed 30 s per 24 hr.
analog integrated circuit device data freescale semiconductor 11 33932 functional description introduction functional description introduction the 33932 has two identical h-bridge drivers in the same package. the only connection that is shared internally is the analog ground (agnd). this description is given for the h- bridge a half of the total device. however, the h-bridge b half will exhibit identical behavior. numerous protection and operational features (speed, torque, direction, dynamic breaking, pwm control, and closed-loop control) make the 33932 a very attractive, cost- effective solution for controlling a broad range of small dc motors. the 33932 outputs are capable of supporting peak dc load currents of up to 5.0 a from a 28 v v pwr source. an internal charge pump and gate drive circuitry are provided that can support external pwm frequencies up to 11 khz. the 33932 has an analog feedback (current mirror) output pin (the fb pin) that provides a constant-current source ratioed to the active high side mosfet s ? current. this can be used to provide ?real time? mo nitoring of output current to facilitate closed-loop operat ion for motor speed/torque control, or for the detection of open load conditions. two independent inputs, in1 and in2, provide control of the two totem-pole half-bridge outputs. two independent disable inputs, d1 and en/ d2 , provide the means to force the h-bridge outputs to a high-impedance state (all h-bridge switches off). the en/ d2 pin also controls an enable function that allows the ic to be placed in a power-conserving sleep mode. the 33932 has output current lim iting (via constant off- time pwm current regu lation), output short-circuit detection with latch-off, and over-tem perature detection with latch- off. once the device is latched-off due to a fault condition, either of the disable inputs (d1 or en/ d2 ), or v pwr must be ?toggled? to clear the status flag. current limiting (load current regulation) is accomplished by a constant-off time pwm method using current limit threshold triggerin g. the current limiting scheme is unique in that it incorpor ates a junction temperature- dependent current limit threshold. this means that the current limit threshold is ?reduced to around 4.2 a? as the junction temperature increa ses above 160c. when the temperature is above 175c, over-temperature shutdown (latch-off) will occur. this co mbination of features allows the device to continue operating for short periods of time (< 30 seconds) with unexpected loads, while still retaining adequate protection for both the device and the load. functional pin description power ground and analog ground (pgnd and agnd) the power and analog ground pins should be connected together with a very low-impedance connection. positive power supply (vpwr) vpwr pins are the power supply inputs to the device. all vpwr pins must be connected together on the printed circuit board with as short as possible traces, offering as low an impedance as possible between pins. status flag ( sf ) this pin is the device fault st atus output. this output is an active low open drain structure requiring a pull-up resistor to v dd . the maximum v dd is < 7.0 v. refer to table 5, truth table , page 15 for the sf output status definition. input 1,2 and disable input 1 (in1, in2, and d1 ) these pins are input control pins used to control the outputs. these pins are 3.0 v/ 5.0 v cmos-compatible inputs with hysteresis. in1 and in2 independently control out1 and out2, respectively. d1 input is used to tri-state disable the h-bridge outputs. when d1 is set (d1 = logic high) in the disable state, outputs out1 and out2 are both tri-state disabled; however, the rest of the device circuitr y is fully operational and the supply i pwr(standby) current is reduced to a few ma. refer to table 3, static electrical characteristics , page 6 . h-bridge output (out1, out2) these pins are the outputs of the h-bridge with integrated free-wheeling diodes. the bridge output is controlled using the in1, in2, d1, and en/ d2 inputs. the outputs have pwm current limiting above the i lim threshold. the outputs also have thermal shutdown (tri-state latch-off) with hysteresis as well as short circuit latch-off protection. a disable timer (time t b ) is incorporated to distinguish between load currents that are higher than the i lim threshold and short circuit currents. this timer is activated at each output transition. charge pump capacitor (ccp) this pin is the charge pump ou tput pin and connection for the external charge pump reservoir capacitor. the allowable value is from 30 to 100 nf. this capacitor must be connected from the ccp pin to the vpwr pin. the device cannot operate properly without the external reservoir capacitor.
analog integrated circuit device data 12 freescale semiconductor 33932 functional description functional pin description enable input/disable input 2 (en/ d2 ) ) the en/ d2 pin performs the same function as d1 pin, when it goes to a logic low the outputs are immediately tri- stated. it is also used to place the device in a sleep mode so as to consume very low currents. when the en/ d2 pin voltage is a logic low state, the device is in the sleep mode. the device is enabled and fully operational when the en pin voltage is logic high. an internal pull-down resistor maintains the device in sleep mode in the event en is driven through a high-impedance i/o or an unpowered microcontroller, or the en/ d2 input becomes disconnected. feedback (fb) the 33932 has a feedback output (fb) for ?real time? monitoring of h-bridge high-side output currents to facilitate closed-loop operation for motor speed and torque control. the fb pin provides current sensing feedback of the h-bridge high side drivers. wh en running in the forward or reverse direction, a ground-ref erenced 0.24% of load current is output to this pin. through the use of an external resistor to ground, the proportional feedback current can be converted to a proportional voltage equivalent and the controlling microcontroller can ?read? the current proportional voltage with its analog-to-digital converter (adc). this is intended to provide the user with only firs t-order motor current feedback for motor torque control. the resistance range for the linear operation of the fb pin is 100 < r fb < 300 . if pwm-ing is implemented using the disable pin input (only d1), a small filter capacitor (~1.0 f) may be required in parallel with the r fb resistor to ground for spike suppression.
analog integrated circuit device data freescale semiconductor 13 33932 functional description functional internal block description functional internal block description figure 10. functional internal block diagram analog control and protection circuitry: an on-chip voltage regulator supplies the internal logic. the charge pump provides gate drive for the h-bridge mosfets. the current and temperature sense circuitry provides detection and protecti on for the output drivers. output undervoltage protection shuts down the mosfets. gate control logic: the 33932 is a monolithic h-bridge power ic designed primarily for any low-voltage dc servo motor control application within the current and voltage limits stated for the device. two independent inputs provide polarity control of two half-bridge totem-pole outp uts. two independent disable inputs are provided to force the h-bridge outputs to tri-state (high impedance off-state). h-bridge output drivers: out1 and out2 the h-bridge is the power out put stage. the current flow from out1 to out2 is reversible and under full control of the user by way of the input contro l logic. the output stage is designed to produce full lo ad control under all system conditions. all protective and co ntrol features are integrated into the control and protection blocks. the sensors for current and temperature are integrated directly into the output mosfet for maximum accuracy and dependability. mc33932 - functional block diagram analog control & protection out1 - out2 out3 - out4
analog integrated circuit device data 14 freescale semiconductor 33932 functional device operation operational modes functional device operation operational modes figure 11. operating states pwm current limiting 9.0 6.5 typical short-circuit detection threshold typical current limit threshold hard short detect ion and latch-off 0 in1 or in2 in2 or in1 in1 or in2 in2 or in1 in1 in2 [1] [0] [1] [0] [1] [0] [1] [0] outputs tri-stated outputs tri-stated outputs operation (per input control condition) time sf logic out en/d2 logic in d1 logic in in n logic in i load output current (a) high current load being regulated via constant-off-time pwm moderate current load
analog integrated circuit device data freescale semiconductor 15 33932 functional device operation logic commands and registers logic commands and registers figure 12. 33932 power stage operation table 5. truth table the tri-state conditions and the stat us flag are reset using d1 or d2 . the truth table uses the foll owing notations: l = low, h = high, x = high or low, and z = high-impedance. all output power transistors are switched off. device state input conditions status outputs en/ d2 d1 in1 in2 sf out1 out2 forward h l h l h h l reverse h l l h h l h free wheeling low h l l l h l l free wheeling high h l h h h h h disable 1 (d1) h h x x l z z in1 disconnected h l z x h h x in2 disconnected h l x z h x h d1 disconnected h z x x l z z under-voltage lockout (29) h x x x l z z over-temperature (30) h x x x l z z short-circuit (30) h x x x l z z sleep mode en/ d2 l x x x h z z en/ d2 disconnected z x x x h z z notes 29. in the event of an under-voltage condition, the outputs tr i-state and status flag is set logic low. upon under-voltage recovery, status flag is reset automatica lly or automatically cleared and the output s are restored to their original operating condition. 30. when a short-circuit or over-temperat ure condition is detected, the power outputs are tri-state latched-off independent of the input signals and the status flag is latc hed to logic low. to reset from this condi tion requires the toggling of either d1, en/ d2 , or v pwr . out1 out2 pgnd v pw r v pw r pgnd load load current forward off on on off out1 out2 pgnd off on on off v pwr v pw r pgnd load load current reverse out1 out2 pgnd v pwr v pwr pgnd load load current high-side recirculation (forward) on off on off out1 out2 pgnd v pwr v pwr pgnd load load current low-side recirculation (forward) on on off off
analog integrated circuit device data 16 freescale semiconductor 33932 functional device operation protection and di agnostic features protection and diagnostic features short-circuit protection if an output short-circuit c ondition is detected, the power outputs tri-state (latch-off) independent of the input (in1 and in2) states, and the fault status output flag ( sf ) is set to logic low. if the d1 input changes from logic high to logic low, or if the en/ d2 input changes from logic low to logic high, the output bridge will become operational again and the fault status flag will be reset (cleared) to a logic high state. the output stage will always switch into the mode defined by the input pins (in1, in2, d1, and en/ d2 ), provided the device junction temperature is within the specified operating temperature range. internal pwm current limiting the maximum current flow under normal operating conditions should be less than 5.0 a. the instantaneous load currents will be limited to i lim via the internal pwm current limiting circuitry. when the i lim threshold current value is reached, the output stages are tri-stated for a fixed time (t a ) of 20 s typical. depending on the time constant associated with the load characteristics, the output current decreases during the tri-state duration un til the next output on cycle occurs. the pwm current limit threshol d value is dependent on the device junction temperature. when - 40c < t j < 160c, i lim is between the specified minimum/maximum values. when t j exceeds 160c, the i lim threshold decreases to 4.2a. shortly above 175c the device over-temperature circuit will detect t lim and an over-temperature shutdown will occur. this feature implements a gracef ul degradation of operation before thermal shutdown occurs, thus allowing for intermittent unexpected mechanical loads on the motor?s gear-reduction train to be handled. important die temperature excursions above 150 c are permitted only for non-repetitive durations < 30 seconds. provision must be made at th e system level to prevent prolonged operation in the current-foldback region. over-temperature shutdown and hysteresis if an over-temperature conditio n occurs, the power outputs are tri-stated (latched-off) and the fault status flag ( sf ) is set to logic low. to reset from this condition, d1 must change from logic high to logic low, or en/ d2 must change from logic low to logic high. when reset, the output stage switches on again, provided that the junc tion temperature is now below the over-temperature threshold limit minus the hysteresis. important resetting from the fault condition will clear the fault status flag. powering down and powering up the device will also reset the 33932 from the fault condition. output avalanche protection if vpwr were to become an open circuit, the outputs would likely tri-state simultaneous ly due to the disable logic. this could result in an unclamped inductive discharge. the vpwr input to the 33932 should not exceed 40 v during this transient condition, to prevent electrical overstress of the output drivers.this can be accomplished with a zener clamp or mov, and/or an appropriately valued input capacitor with sufficiently low esr (see figure 13 ). figure 13. avalanche protection out1 out2 i/os agnd pgnd bulk low esr cap. vpwr 100nf m v pwr 9
analog integrated circuit device data freescale semiconductor 17 33932 typical applications introduction typical applications introduction a typical application schematic is shown in figure 14 . for precision high-current applic ations in harsh, noisy environments, the v pwr by-pass capacitor may need to be substantially larger. figure 14. 33932 typical application schematic 1/2 device vdd logic supply charge pump gate drive and protection logic current mirrors and constant off-time pwm current regulator vcp ccpa out1 out2 agnda to gates hs1 ls1 hs2 ls2 vpwra vsense ilim pwm hs1 hs2 ls1 ls2 ls2 in1 in2 en/d2 d1 sfa fba pgnda +5.0 v r fb 270 status flag to adc 1.0 f 33 nf v pwr 100 nf 100 f m pgnd
analog integrated circuit device data 18 freescale semiconductor 33932 packaging package dimensions packaging package dimensions for the most current pa ckage revision, visit www.freescale.com and perform a keyword sear ch using the 98axxxxxxxxx listed below. vw suffix 44-pin 98arh98330a revision b
analog integrated circuit device data freescale semiconductor 19 33932 packaging package dimensions vw suffix 44-pin 98arh98330a revision b
analog integrated circuit device data 20 freescale semiconductor 33932 revision history revision history revision date description 1.0 8/2007 ? initial release 2.0 8/2008 ? added parameters (tbd) for change pump voltages in table 3. 3.0 11/2008 ? changed maximum r ds(on) from 225 to 235m . ? changed peak package reflow temperature during reflow (7) , (8) ? changed approximate junction-to case thermal resistance (9)
mc33932 rev. 3.0 1/2009 information in this document is provided solely to enable system and software implementers to use freescale semiconduc tor products. there are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. freescale semiconductor reserves the right to make changes without further notice to any products herein. freescale semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does freescale semiconductor assume any liability ar ising out of the application or use of any product or circuit, and specifically discl aims any and all liability, including without limitation consequential or incidental damages. ?typical? parameters that may be provided in freescale semiconductor data s heets and/or specifications can and do vary in different applications and actual performance may vary over time. all operating parameters, including ?typicals?, must be validated for each customer application by customer?s technical experts. freescale se miconductor does not convey any license under its patent rights nor the rights of others. freescale semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the fa ilure of the freescale semiconductor product could create a situation where personal injury or death may occur. should buyer purchase or use freescale semiconductor products for any such unintended or unauthorized application, buyer shall indemni fy and hold freescale semiconductor and its officers, employees, subsidiaries, affili ates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that freescale semiconductor was negligent regarding the design or manufacture of the part. freescale? and the freescale logo are trademarks of freescale semiconductor, inc. all other product or service names are the property of their respective owners. ? freescale semiconductor, inc., 2009. all rights reserved. how to reach us: home page: www.freescale.com web support: http://www.freescale.com/support usa/europe or locations not listed: freescale semiconductor, inc. technical information center, el516 2100 east elliot road tempe, arizona 85284 +1-800-521-6274 or +1-480-768-2130 www.freescale.com/support europe, middle east, and africa: freescale halbleiter deutschland gmbh technical information center schatzbogen 7 81829 muenchen, germany +44 1296 380 456 (english) +46 8 52200080 (english) +49 89 92103 559 (german) +33 1 69 35 48 48 (french) www.freescale.com/support japan: freescale semiconductor japan ltd. headquarters arco tower 15f 1-8-1, shimo-meguro, meguro-ku, tokyo 153-0064 japan 0120 191014 or +81 3 5437 9125 support.japan@freescale.com asia/pacific: freescale semiconductor hong kong ltd. technical information center 2 dai king street tai po industrial estate tai po, n.t., hong kong +800 2666 8080 support.asia@freescale.com for literature requests only: freescale semiconductor literature distribution center p.o. box 5405 denver, colorado 80217 1-800-441-2447 or 303-675-2140 fax: 303-675-2150 ldcforfreescalesemiconductor@hibbertgroup.com

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